Fracture aware OPC

ABSTRACT

The present disclosure describes an OPC method of preparing data for forming a mask. The method includes setting a plurality of dissection points at the main feature and further includes setting a target point at the main feature. The method includes arranging the two dissection points crossing the main feature symmetrically each other. The method includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer. The method includes dividing the main feature into a plurality of segments using the dissection points. The method includes performing an OPC convergence simulation to a target point. The method includes correcting the segments belonging to an ambit of the target point and further includes correcting the segment shared by two ambits.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experiencedexponential growth. Technological advances in IC materials and designhave produced generations of ICs where each generation has smaller andmore complex circuits than the previous generation. In the course of ICevolution, functional density (i.e., the number of interconnecteddevices per chip area) has generally increased while geometry size(i.e., the smallest component (or line) that can be created using afabrication process) has decreased. This scaling down process generallyprovides benefits by increasing production efficiency and loweringassociated costs. Such scaling down has also increased the complexity ofprocessing and manufacturing ICs and, for these advances to be realized,similar developments in IC processing and manufacturing are needed.

For example, light diffraction in an optical lithography system becomesan obstacle for further scaling down the feature size. Common techniquesused to decrease the light diffraction impact include using opticalproximity correction (OPC), a phase shift mask (PSM), and an immersionoptical lithography system. A fracture is performed on an IC designlayout feature making a mask after the OPC during. The fracture may beexecuted at asymmetrical dissection points of the IC design layoutfeature. However, small fragments are created by the asymmetricaldissection points. Therefore mask fidelity is degraded by the smallfragments and further mask performance is impacted.

Accordingly, what is needed is a method to improve the OPC to reducenumber of the small fragments after performing the OPC to an IC designlayout data.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with accompanying figures. It is emphasized that,in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposeonly. In fact, the dimension of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIG. 1 represents a diagram of an optical lithography system forbenefitting from one or more embodiments of the present disclosure.

FIG. 2 is a flow chart of making a mask for implementing one or moreembodiments of the present disclosure.

FIGS. 3-5 represent an example of fracturing an integrated circuit (IC)design layout according to one or more embodiments of the presentdisclosure.

FIG. 6 is a flow chart of making a mask for implementing one or moreembodiments of the present disclosure.

FIGS. 7-9 represent an example of fracturing an integrated circuit (IC)design layout according to one or more embodiments of the presentdisclosure.

FIG. 10 is an example of applying an area-based correction of a method400 to a layout according to one or more embodiments of the presentdisclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the disclosure.Specific examples of components and arrangements are described below tosimplify the present disclosure. These are, of course, merely examplesand are not intended to be limiting. For example, the formation of afirst feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Referring now to FIG. 1, an optical lithography system 100 is an exampleof a system that can benefit for one or more embodiments of the presentdisclosure. The optical lithography system 100 includes a light source102, a light 104, a condense lens 106, a photomask 108, a mask stage110, a projection lens 112, a substrate stage 114, a substrate 116 and aresist film 118. However, other configurations and inclusion or omissionof the device may be possible. In the present disclosure, the system 100is also referred as a stepper or a scanner, and the photo mask 108 isalso referred to as a mask, a photo mask, or a reticle. In the presentembodiment, the light source 102 includes a radiation source providingthe light 104 having a wavelength range from UV to DUV. For example, amercury lamp provides UV wavelength, such as G-line (436 nm) or I-line(365 nm), or an excimer laser provides DUV wavelength, such as 248 nm,193 nm, or 157 nm. The condense lens 106 is configured to guide thelight 104 to the photomask 108. The photomask 108 blocks a portion ofthe light 204 and provides an aerial image of the light 104 to form thepatterned light 104. The photomask 108 may be a binary mask (BIM), asuper binary mask (SBIM), or a phase shift mask (PSM), which includes analternative phase shift mask (alt. PSM) or an attenuated phase shiftmask (att. PSM). The photo mask 108 is positioned on the mask stage 110.The mask stage 110 includes a plurality of motors, roller guides, andtables; secures the photomask 108 on the mask stage 110 by vacuum; andprovides accurate position and movement of the photomask 208 in X, Y,and Z directions during alignment, focus, leveling and exposureoperation in the optical lithography system 100. The projection lens 112includes a magnification lens for reducing the pattern image provided bythe photomask 108 and guides the patterned light 104 a to the resistfilm 118 deposited on the substrate 116 secured by the substrate stage114. The substrate stage 114 includes motors, roller guides, and tables;secures the substrate 116 by vacuum; and provides accurate position andmovement of the substrate 116 in X, Y, and Z directions duringalignment, focus, leveling and exposure operations in the opticallithography system 100 so that the image of the photomask is transferredonto the substrate in a repetitive fashion (though other lithographymethods are possible). The optical lithography system 100, or portionsthereof, may include additional items, such as a vacuum system and/or acooling system.

Continuing with the present embodiments, the substrate 116 depositedwith the resist film 118 is loaded on the substrate stage 114 forexposing by the patterned light 104. The resist film 118 includes apositive tone resist or a negative tone resist. The substrate 116includes a wafer substrate. The wafer substrate includes a siliconwafer. Alternatively or additionally, the wafer may includes anotherelementary semiconductor, such as germanium; a compound semiconductorincluding silicon carbide, gallium arsenic, gallium phosphide, indiumphosphide, indium arsenide, and/or indium antimonide; an alloysemiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP,and/or GaInAsP. In yet another alternative, the wafer is a semiconductoron insulator (SOI). A plurality of conductive and non-conductive thinfilms may be deposited on the wafer. For example, the conductive thinfilms may include a metal such as aluminum (Al), copper (Cu), tungsten(W), nickel (Ni), titanium (Ti), gold (Au), and platinum (Pt), or alloysthereof. The insulator film may include silicon oxide or siliconnitride. The substrate may be a blank mask substrate that includes a lowthermal expansion material such as quartz, silicon, silicon carbide, orsilicon oxide-titanium oxide compound.

Referring to FIG. 2, a flow chart of a method 200 illustrates oneembodiment of a mask making process. In the present disclosure, the termmask, photomask and reticle are used to refer to the same item. Themethod 200 begins at step 210 by providing or receiving an IC designlayout data (or IC design layout pattern) from a designer. The designercan be a separate design house or can be part of a semiconductorfabrication facility (fab) for making IC productions according to the ICdesign layout. In various embodiments, the semiconductor fab may becapable of making photomasks, semiconductor wafers, or both. The ICdesign layout includes various geometrical patterns designed for an ICproduct and based on a specification of the IC product.

The IC design layout is presented in one or more data files having theinformation of the geometrical patterns. In one example, the IC designlayout is expressed in a “gds” format. The designer, based on thespecification of the product to be manufactured, implements a properdesign procedure to carry out the IC design layout. The design proceduremay include logic design, physical design, and/or place and route. As anexample, a portion of the IC design layout includes various IC features(also referred to as main features), such as active region, gateelectrode, source and drain, metal lines and vias of an interlayerinterconnection, and openings for bonding pads, to be formed in and on asemiconductor substrate (such as a silicon wafer) and various materiallayers disposed over the semiconductor substrate. The IC design layoutmay include certain assist features, such as for imaging effect,processing enhancement, and/or mask identification information. In thepresent disclosure a feature referred to as a segment.

As shown in FIG. 2, the method 200 proceeds to step 220 for preparingdata process. The step 220 includes running a design rule check (DRC) toverify the IC design layout satisfying a semiconductor manufactureprocess of the fab. The step 220 also includes performing a logicoperation (LOP) with small bias corrections requested by the fab. Thestep 220 further includes step 224 and step 226. The step 222 includessetting a plurality of dissection points at the IC design feature. Thestep 224 includes setting a target point at the IC design feature.Dissection points and target points are discussed further below, withreference to FIGS. 3-5.

After step 220, the method 200 proceeds to step 230 for applying anoptical proximity correction (OPC) modification to the LOP modifieddesign layout data. The step 230 includes dividing the IC design featureinto a plurality of segments using the dissection points. The step 230also includes adjusting a size of the segment based on an OPC rule or anOPC model. The step 230 further includes step 232 and step 234 forevaluating OPC result. The step 232 includes running an OPC simulationbased on the size of the segment modified by the OPC. The step 234includes evaluating an OPC convergence to the target (design ICfeature). If the OPC convergence is not satisfied, the method 200 backsto step 230 by moving the segment or adjusting the size of the segmentagain. This cycle can repeat many times until the satisfied OPCconvergence is reached.

After the satisfied OPC convergence is reached at step 234, the method200 proceeds to step 240 for executing a post data process. The step 240includes performing a mask rule check (MRC) to verify the OPC modifiedfeature satisfying the semiconductor manufacture process of the fab. Inthe present embodiments, the MRC verifies a minimum line width of theOPC modified features, or a minimum space between two adjacent OPCmodified features is within capability of the semiconductor manufactureprocess of the fab. The step 240 includes fracturing the complicated OPCmodified design layout into a plurality of simple shapes for the maskwriter. For example, a complex polygon is fractured into rectangles,trapezoids, or combination thereof. The step 240 also includesconverting the fractured OPC modified IC design layout data to electronbeam writer format data for a mask writer. The converted IC designlayout data proceeds to step 250 for masking a mask (or fabricating amask). Creating a plurality of designed layout patterns on the mask iscarried out by an electron beam writer, an ion beam writer or a laserbeam writer. Additional steps can be provided before, during, and afterthe method 200, and some the steps described can be replaced,eliminated, or moved around for additional embodiments of the method200.

In one embodiment of the present disclosure, the mask may be a binarymask (BIM), a super binary mask (SBIM), or a phase shift mask (PSM),which includes an alternative phase shift mask (alt. PSM) or anattenuated phase shift mask (att. PSM). In another embodiment, the maskmay be a transmissive mask used under ultra-violet light (e. g. G-line,or I-line) or under deep ultra-violet light (DUV), or a reflective maskused under extreme ultra-violet light (EUV).

Referring now to FIGS. 3-5, an IC design layout 300 is an example forimplementing one or more embodiments of the present disclosure. As shownthe FIG. 3, the IC design layout 300 includes feature 302, feature 304,feature 306, and feature 308. However, other configurations andinclusion or omission of the IC design layout may be possible. In thepresent disclosure, a feature is also referred to as a main feature, apolygon, or a pattern. As descried at the step 220 of the method 200shown in FIG. 2, the pre-data process is applied to the layout 300 atthe step 200 of the method 200. The pre-data process includes settingthe dissection points on the features 302, 304, 306, and 308. FIG. 4represents an example of setting the dissection points on the layout300. The dissection points are presented in a short slash line shown inFIG. 4. Dissection points 302 a and dissection points 302 b are appliedto the feature 302, dissection points 304 a and dissection points 304 bare applied to the feature 304, dissection points 306 a and dissectionpoints 306 b are applied to the feature 306, and dissection points 308 aand dissection points 308 b are applied to the feature 308. Thedissection points are determined by a critical dimension (CD) of thefeature, a shape of the feature, and/or an environment of the feature.Other factors, such as exposing process and exposing tool of the fab,may also determine the dissection points. As shown in FIG. 4, dissectionpoints 302 a and 302 b are symmetrically distributed across the feature302. The dissection points 304 a and 304 b are symmetrically distributedacross feature 304 and the dissection points 306 a and 306 b are alsosymmetrically distributed across the feature 306 respectively. However,dissection points 308 a and 308 b are not symmetrically distributedacross the feature 308.

In the present embodiments, the OPC technique is applied to the layout300 at step 230 of the method 200 shown in FIG. 2. The OPC techniqueincludes dividing the feature into a plurality of segments using thedissection points and adjusting the size of the segments. At step 240 ofthe method 200, the modified segments by the OPC technique are fracturedto form a plurality of rectangles and/or trapezoids for the mask writermaking the mask. The OPC technique also includes running a simulation tothe modified segment to verify an OPC convergence to a feature of thedesign feature.

FIG. 5 illustrates an example of fracturing the layout 300 forimplementing one or more embodiments of the present disclosure. The ICdesign features are modified by the OPC technique and fractured into therectangles. Fractured features 302 c, 304 c, 306 c, and 308 c arederived from the corresponding features 302, 304, 306 and 308 of thelayout 300. The fractured features 302 c, 304 c, 306 c and 308 c includerectangles. As shown in FIGS. 4-5, the fracturing is performed at eachdissection point crossing the feature in horizontal or verticaldirection. Each dissection point generated one fracturing line. In oneembodiment, if the dissection points are symmetrically distributedacross the feature, two symmetrical dissection points across the featureform two superimposed fracturing lines and therefore one fracturing lineis formed from two symmetrical dissection points. The fractured features302 c, 304 c and 306 c are fractured at the symmetric dissection points.In another embodiment, if the dissection points are asymmetricallydistributed across the feature, more fracturing lines are formed, andtherefore a small fragment is formed. The fractured feature 308 c shownin FIG. 5 is an example of the asymmetrical dissection points across thefeature 308. The fractured feature 308 c includes a plurality of thesmall fragments. The mask integrity and performance are seriouslyimpacted by the small fragments caused by the asymmetrical dissectionpoints.

Referring now to FIG. 6, a flow chart of a method 400 for making a maskis illustrated according to one or more embodiments of the presentdisclosure. The method 400 begins at step 410 by providing or receivingan IC design layout data (or IC design layout pattern) from a designer.The IC design layout data includes a main feature. In the presentdisclosure, a main feature is also referred to as a pattern or afeature. The method 400 proceeds to step 420 for performing pre-dataprocess. The step 420 includes running the DRC to verify the IC designlayout satisfying a semiconductor manufacture process of the fab. Thestep 420 also includes performing a logic operation (LOP) with smallbias corrections to the main feature requested by the fab. The step 420further includes step 422 and step 224. The step 222 includes setting aplurality of dissection points at the IC design feature. The step 424includes setting a target point at the main feature.

As shown in FIG. 6, after step 220, the method 400 proceeds to step 430for applying the OPC modification to the IC design layout data. The step430 includes dividing the IC design feature into a plurality of segmentsusing the dissection points. The step 430 also includes adjusting a sizeof the segment based on the OPC rule or the OPC model. The step 430further includes step 432, step 434, and step 436. The step 432 includesinspecting the dissection points on the main feature and making sure twodissection points across the main feature symmetrically are distributedacross the main feature. If the two dissection points are notdistributed symmetrically across the main feature, the two dissectionpoints are adjusted so that the two dissection points are symmetricallydistributed across the main feature. The step 432 also includes making adistance between two adjacent dissection points at same side of the mainfeature equals to a maximum electron beam writer resolution. Forexample, the maximum beam resolution is 10 nm for a typical mask writer.Therefore, a number of the fractured segments are reduced. The step 434includes running an OPC simulation based on the OPC modified segments.The step 436 includes evaluating an OPC convergence to the target(design IC feature). If the OPC convergence is not satisfied, the method400 backs to step 434 by moving the segment or adjusting the size of thesegment again. This cycle can repeat many times until the satisfied OPCconvergence is reached. In present embodiments, the step 434 includesperforming an area correction. This will discuss in more detail in lateparagraph of this present disclosure.

After the satisfied OPC convergence is reached at step 436, the method400 proceeds to step 440 for executing a post data process. The step 440includes performing a mask rule check (MRC) to verify the OPC modifiedfeature satisfying the semiconductor manufacture process of the fab. Inthe present embodiments, the MRC verifies a minimum line width of theOPC modified features, and/or a minimum space between two adjacent OPCmodified features is within capability of the semiconductor manufactureprocess of the fab. The step 440 is the same as 240. The step 450includes fracturing the complicated OPC modified design layout into aplurality of simple shapes for the mask writer. The converted IC designlayout data proceeds to step 450 for masking a mask (or fabricating amask). Creating a plurality of designed layout patterns on the mask iscarried out by an electron beam writer, an ion beam writer or a laserbeam writer. Additional steps can be provided before, during, and afterthe method 400, and some the steps described can be replaced,eliminated, or moved around for additional embodiments of the method400.

Referring now to FIGS. 7-9, an example of fracturing a layout 500 isillustrated according to one or more embodiments of the presentdisclosure. The layout 500 includes a main feature 502. As shown in FIG.7, dissection 502 a and dissection 502 b are set at the main feature 502using the method 400 at step 422 as shown in FIG. 6. The dissection 502a is set at one side of the main feature 502 and the dissection 502 b isset at another side of the main feature 502 b. The dissection 502 a isasymmetrical to the dissection 502 b across the main feature 502. If theOPC is applied to the main feature 502 based on the dissection 502 a andthe dissection 502 b, a plurality of small fragments are formed afterthe OPC and the fractured segment as shown in FIG. 5. The maskperformance and integrity based on the dissection 502 a and dissection502 b at the main feature 502 are impacted by the small fragments.

As shown in FIG. 8, one embodiment of the present disclosure ispresented. A dissection 502 c and dissection 502 d are set at the mainfeature 502 using method 400 at step 432 as shown in FIG. 6. Thedissection 502 c is set at one side of the main feature 502 and thedissection 502 d is set at another side of the main feature 502 b. Thedissection 502 c and the dissection 502 d are formed by modifying thedissection 502 a and the dissection 502 b respectively using thefracture aware dissection as described at step 432 of the method 400.The dissection 502 c is symmetrical to the dissection 502 d across themain feature 502. After the OPC is applied to the main feature 502 basedon the dissection 502 c and the dissection 502 d. An OPC modified mainfeature 502 e is formed. As shown in FIG. 9, because the dissection 502c is symmetrical to the dissection 502 d across the main feature 502shown in FIG. 8, after fracturing, no small fragment is formed.Furthermore, the dissection 502 c and the dissection 502 d are set usingthe maximum resolution of the electron beam writer, and thereforeoverall dissection is also reduced. For example, a layout generatesabout 370,000 fracture shots (segments) for the electron beam writerusing the method 200. Contour critical dimension uniformity (CDU) 3sigma is about 1.62. In another example, the same layout generates about290,000 fracture shots (segments) for the electron beam writer using themethod 400. The contour CDU 3 sigma is about 1.54. The fracture shotsare reduced by about 20% and the contour CDU 3 sigma is improved byabout 14%.

Referring now to FIG. 10, an example of applying an area-basedcorrection of the method 400 to a layout 600 is presented according toone or more embodiments of the present disclosure. The layout 600includes features 602, 604, 608, 610, 612, and 614. As shown in FIG. 10,a plurality of symmetrical dissection points is set at the features602-614. The OPC technique is applied to the features 604-614 togenerate the corresponding modified OPC feature for each feature. In thepresent embodiments, a target point 624 is set at the feature 604 and atarget point 628 is set at the feature 608 as shown in FIG. 10. Thetarget points are used to verify the corresponding modified OPC featureconvergence for the feature. For example, the target point 624 is usedto verify OPC convergence for the feature 604 and the target point 628is used to verify OPC convergence for the feature 608. In the presentembodiments, each target point also has an influence ambit. For example,the target point 624 has an inference ambit 624 a and the target point628 has an inference ambit 628 a.

In the present embodiments, when verifying the OPC convergence for thefeature, all the segments generated from the symmetrical dissectionpoints are considered and corrected simultaneously. The segmentoverlapped (shared) by the ambits of multiple target points is correctedby a weighed factor. The area-based correction approach provides moredegree of freedom (more segments) for the OPC convergence while notdegrading the mask fidelity.

For example, as shown in FIG. 10, the correction for the OPC convergenceto the target 624 of the feature 604 is presented. All the segmentsbelonging to the ambit 624 a of the target 624 are corrected. Thesegments to be corrected for the OPC convergence to the target 624 arenot only from the feature 604, but also from the feature 608 and thefeature 610. All the segments located in the ambit 624 a are underconsideration for correction. A segment 632 is overlapped by the ambit624 a of the target 624 and the ambit 628 a of the target 628. Acorrection of the segment 632 is based on both the OPC convergence ofthe feature 604 and the OPC convergence of the feature 608.

In another example, the correction for the OPC convergence of the target628 of the feature 608 shown in FIG. 10, all the segments belonging tothe ambit 628 a of the target 628 are corrected. The segments to becorrected for the OPC convergence of the target 628 are not only fromthe feature 608, but also from the feature 606. A segment 632 isoverlapped by the ambit 624 a of the target 624 and the ambit 628 a ofthe target 628. A correction of the segment 632 is based on both the OPCconvergence of the feature 604 and the OPC convergence of the feature608.

Thus, the present disclosure describes a method of forming a mask. Themethod includes receiving an integrated circuit (IC) design layoutincluding a main feature, performing a pre-data preprocess, modifyingthe IC design layout using an optical proximity correction (OPC)technique, fracturing the OPC modified IC design layout into a polygon,and writing the OPC modified IC design layout data onto a mask substrateusing a mask writer. The method includes setting a plurality ofdissection points at the main feature and further includes setting atarget point at the main feature. The method includes arranging the twodissection points crossing the main feature symmetrically each other sothat two fracturing lines generated by the two dissection pointssuperimpose to form one fracturing line. The method includes separatingtwo adjacent dissection points at one side of the main feature by amaximum resolution of the mask writer. The method includes dividing themain feature into a plurality of segments using the dissection point.The method includes adjusting size of the segment. The method includesperforming an OPC convergence simulation to the target point. The methodincludes correcting the segments belonging to an ambit of the targetpoint and further includes correcting the segment shared by two ambits.

The present disclosure also describes a method of preparing data formaking a mask. The method includes receiving an integrated circuit (IC)design layout comprising a main feature, performing a pre-data process,modifying the IC design layout by applying an optical proximitycorrection (OPC) technique to the IC design layout data, and applying apost data treatment. The performing the pre-data process includessetting a target point at the main feature. The applying the post datatreatment includes fracturing the OPC modified IC design layout into apolygon. The method further includes writing the OPC modified IC designlayout onto a mask substrate using a mask writer. The method includesarranging two dissection points symmetrically across the main featureand further includes separating two adjacent dissecting points at sameside of the main feature by maximum resolution of the mask writer. Themethod includes running an OPC convergence simulation to the targetpoint. The target point has an ambit which includes a plurality ofsegments. The method includes correcting the segment belongs to theambit and further includes correcting the segment shared by two ambits.

In another embodiment, a method of preparing data for making a mask ispresented. The method includes receiving an integrated circuit (IC)design layout data comprising a main feature, performing a pre-dataprocess, modifying the IC design layout by applying an optical proximitycorrection (OPC) technique to the IC design layout data, and applying apost data process. The applying the post data process includesfracturing the OPC modified IC design layout into a polygon. Theperforming the pre-data process includes setting a target point at themain feature. The modifying the IC design layout includes setting twodissection points symmetrically across the main feature, separating twoadjacent dissection points at same side of the main feature by a maximumresolution of a mask writer, forming a segment using the dissectionpoints, running an OPC convergence simulation to the target point,wherein the target point having an ambit including a segment, correctingthe segment belonging to the ambit, and further correcting the segmentshared by two ambit. The method further includes writing the OPCmodified IC design layout onto a substrate using a mask writer.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of making a mask, the method comprising: receiving an integrated circuit (IC) design layout including a main feature; modifying the IC design layout using an optical proximity correction (OPC) technique; applying a post data process, wherein applying the post data process includes fracturing the OPC modified IC design layout into a plurality of discrete polygons; and writing the OPC modified IC design layout data onto a mask substrate using a mask writer; wherein modifying the IC design layout data using OPC includes correcting a segment belonging to an ambit of a target point and correcting a segment shared by two ambits.
 2. The method of claim 1, further comprising performing a pre-data process that includes setting a plurality of dissection points at the main feature.
 3. The method of claim 2, further comprising setting a target point at the main feature.
 4. The method of claim 1, wherein modifying the IC design layout using the OPC includes arranging two dissection points crossing the main feature symmetrically each other so that two fracturing lines generated by the two dissection points superimpose to form one fracturing line.
 5. The method of claim 1, wherein modifying the IC design layout using the OPC includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer.
 6. The method of claim 1, wherein modifying the IC design layout using the OPC includes dividing the main feature into a plurality of segments using a dissection point.
 7. The method of claim 1, wherein modifying the IC design layout data using OPC includes performing an OPC convergence simulation to a target point.
 8. A method of preparing data for making a mask, the method comprising: receiving, using an optical lithography system, an integrated circuit (IC) design layout comprising a main feature; performing a pre-data process, wherein performing the pre-data process includes setting a target point at the main feature; modifying the IC design layout using the target point by applying an optical proximity correction (OPC) technique to the main feature; and applying a post data treatment, wherein applying the post data treatment includes fracturing the OPC modified IC design layout into a plurality of discrete polygons; wherein applying the OPC technique includes correcting a segment belonging to an ambit and correcting a segment shared by two ambits.
 9. The method of claim 8, further comprising writing the OPC modified IC design layout onto a mask substrate using a mask writer.
 10. The method of claim 8, wherein applying the OPC technique to the IC design layout includes arranging two dissection points symmetrically across the main feature.
 11. The method of claim 10, further comprising separating the two adjacent dissecting points at same side of the main feature by maximum resolution of the mask writer.
 12. The method of claim 8, wherein applying the OPC technique to the IC design layout includes running an OPC convergence simulation to the target point.
 13. The method of claim 12, wherein the target point includes an ambit including a plurality of segments.
 14. A method of preparing data for making a mask, the method comprising: receiving, using an optical lithography system, an integrated circuit (IC) design layout data comprising a main feature; performing a pre-data process, wherein performing the pre-data process includes setting a target point at the main feature; modifying the IC design layout by applying an optical proximity correction (OPC) technique to the IC design layout data, wherein modifying the IC design layout includes: setting two dissection points symmetrically across the main feature, separating two adjacent dissection points at same side of the main feature by a maximum resolution of a mask writer, forming a segment using the dissection points, running an OPC convergence simulation to the target point, wherein the target point having an ambit including a segment, correcting the segment belonging to the ambit, and further correcting the segment shared by two ambits; and applying a post data process, wherein applying the post data process includes fracturing the OPC modified IC design layout into a plurality of discrete polygons.
 15. The method of 14, further comprising writing the OPC modified IC design layout onto a substrate using a mask writer. 